An On-Chip Traffic Permutation Network for Multiprocessor System-On-Chip

The Networks on Chip (NoC), due to their flexibility, scalability and high bandwidth features they are considered as on-chip communication fabrics for future multiprocessor systemon-chips(MPSOCs).In this paper the design of a network on chip to support a guaranteed throughput is explained. The close nework topology is used with the three stages of switches and each stage having three switches of 4 ports of inputs and outputs. This network to support guaranteed traffic permutation in multiprocessor system-on-chip applications. The proposed network employs a pipelined circuit-switching approach combined with a dynamic path-setup scheme under a multistage network topology. The dynamic path-setup scheme enables runtime path arrangement for arbitrary traffic permutations. The circuit-switching approach offers a guarantee of permuted data and its compact overhead enables the benefit of stacking multiple networks. Network on chip or network on a chip (NoC or NOC) is a communication subsystem on an integrated circuit, typically between IP cores in a system on a chip (SoC). NoCs are an attempt to scale down the concepts of large scale networks, and apply them to the embedded system on chip domain. Traditional busses are not suitable to the system on chip domain. The fundamental unit of building a Network on Chip is the router, it directs the packets according to a routing algorithm to the desired host. In this project, switch is designed using VERILOG language and simulated with the help of Integrated software environment ( ISE12.2) , and then (3x3) clos topology network is designed.